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| EM78F651N 8-Bit Microcontroller Product Specification DOC. VERSION 1.1 ELAN MICROELECTRONICS CORP. October 2006 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation. Copyright (c) 2006 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS. ELAN MICROELECTRONICS CORPORATION Headquarters: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Flat A, 19F World Tech Centre 95 How Ming Street, Kwun Tong Kowloon, Hong Kong Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk Shenzhen: Elan Microelectronics Shenzhen, Ltd. SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, China Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 USA: Elan Information Technology Group (U.S.A.) 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 U.S.A. Tel: +1 408 366-8225 Fax: +1 408 366-8220 Europe: Elan Microelectronics Corp. (Europe) Siewerdtstrasse 105 8050 Zurich, Switzerland Tel: +41 43 299-4060 Fax: +41 43 299-4079 http://www.elan-europe.com Shanghai: Elan Microelectronics Shanghai, Ltd. 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, China Tel: +86 21 5080-3866 Fax: +86 21 5080-4600 Contents Contents 1 2 3 4 5 6 General Description .................................................................................................. 1 Features ..................................................................................................................... 1 Pin Assignment ......................................................................................................... 2 Pin Description.......................................................................................................... 3 Block Diagram ........................................................................................................... 5 Function Description ................................................................................................ 6 6.1 Operational Registers......................................................................................... 6 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 6.1.9 6.1.10 6.1.11 6.1.12 6.1.13 6.1.14 R0 (Indirect Addressing Register) .......................................................................6 R1 (Timer Clock/Counter) ...................................................................................6 R2 (Program Counter) & Stack ...........................................................................6 R3 (Status Register) ............................................................................................9 R4 (RAM Select Register)...................................................................................9 R5 ~ R7 (Port 5 ~ Port 7) ....................................................................................9 R8 ~ R9 ...............................................................................................................9 RA (Wake- up Control Register)........................................................................10 RB (EEPROM Control Register) .......................................................................10 RC (128 Bytes EEPROM Address) ...................................................................11 RD (128 Bytes EEPROM Data) ........................................................................11 RE (LVD Control Register) ................................................................................11 RF (Interrupt Status Register) ...........................................................................12 R10 ~ R3F .........................................................................................................12 A (Accumulator).................................................................................................13 CONT (Control Register)...................................................................................13 IOC5 ~ IOC7 (I/O Port Control Register) ..........................................................14 IOCA (WDT Control Register) ...........................................................................14 IOCB (Pull-down Control Register) ...................................................................15 IOCC (Open-drain Control Register).................................................................15 IOCD (Pull-high Control Register).....................................................................16 IOCF (Interrupt Mask Register).........................................................................16 6.2 Special Function Registers............................................................................... 13 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.3 6.4 6.5 TCC/WDT & Prescaler ..................................................................................... 17 I/O Ports ........................................................................................................... 18 Reset and Wake-up.......................................................................................... 21 6.5.1 6.5.2 Reset .................................................................................................................21 Status of RST, T, and P of the Status Register..................................................27 6.6 6.7 Interrupt ............................................................................................................ 29 LVD (Low Voltage Detector) ............................................................................. 30 Product Specification (V1.1) 10.20.2006 iii Contents 6.8 Data EEPROM ................................................................................................. 32 6.8.1 Data EEPROM Control Register .......................................................................32 6.8.1.1 RB (EEPROM Control Register) ........................................................32 6.8.1.2 RC (128 Bytes EEPROM Address) ....................................................33 6.8.1.3 RD (128 Bytes EEPROM Data) .........................................................33 Programming Step / Example Demonstration...................................................33 6.8.2.1 Programming Step..............................................................................33 6.8.2.2 Example Demonstration Programs ....................................................34 Oscillator Modes................................................................................................35 Crystal Oscillator/Ceramic Resonators (Crystal)...............................................35 External RC Oscillator Mode.............................................................................37 Internal RC Oscillator Mode ..............................................................................38 6.8.2 6.9 Oscillator .......................................................................................................... 35 6.9.1 6.9.2 6.9.3 6.9.4 6.10 Code Option Register...................................................................................... 39 6.10.1 Code Option Register (Word 0).........................................................................39 6.10.2 Customer ID Register (Word 2).........................................................................43 6.11 Power-on Considerations ................................................................................ 43 6.12 External Power-on Reset Circuit ..................................................................... 43 6.13 Residue-Voltage Protection............................................................................. 44 7 8 9 10 6.14 Instruction Set ................................................................................................. 45 Timing Diagrams ..................................................................................................... 48 Absolute Maximum Ratings ................................................................................... 49 DC Electrical Characteristic ................................................................................... 49 AC Electrical Characteristic ................................................................................... 52 APPENDIX A B C Package Type........................................................................................................... 53 ICE 652N Output Pin Assignment (JP 3) ............................................................... 54 EM78F651N Program Pin: ...................................................................................... 54 Specification Revision History Doc. Version 1.0 Initial version 1. Modified the General Description, Pin Assignment and Features sections. 2. Added Green Product Information. 3. Modified the Functional Block Diagram. Revision Description Date 2006/09/20 1.1 2006/10/20 iv * Product Specification (V1.1) 10.20.2006 EM78F651N 8-Bit Microcontroller 1 General Description The EM78F651N is an 8-bit microprocessor designed and developed with low-power, high-speed CMOS technology and high noise immunity. It has an on-chip 1Kx13-bit Electrical Flash Memory and 128x8-bit in system programmable EEPROM. It provides three protection bits to prevent intrusion of user's Flash memory code. Twelve Code option bits are also available to meet user's requirements. With its enhanced Flash-ROM feature, the EM78F651N provides a convenient way of developing and verifying user's programs. Moreover, this Flash-ROM device offers the advantages of easy and effective program updates, using development and programming tools. User can avail of the ELAN Writer to easily program his development code. 2 * * * * * * * * * * * * * * * * * * Features CPU configuration 1Kx13 bits on chip ROM 80x8 bits on chip registers (SRAM) 128 bytes in-system programmable EEPROM *Endurance: 100,000 write/erase cycles More than 10 years data retention 5-level stacks for subroutine nesting Less than 2 mA at 5V/4MHz Typically 20 A, at 3V/32kHz Typically 2 A, during sleep mode Peripheral configuration * * * * * * 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt Power down (Sleep) mode *Vdd power monitor and supports low voltage detector interrupt flag 4 programmable Level Voltage Detector (LVD) Three security registers to prevent intrusion of Flash memory codes One configuration register to accommodate user's requirements 2/4/8/16 clocks per instruction cycle selected by code option I/O port configuration 2 bidirectional I/O ports Wake-up port : P6 8 Programmable pull-down I/O pins 8 programmable pull-high I/O pins 8 programmable open-drain I/O pins External interrupt : P60 Single instruction cycle commands Four Crystal range in Oscillator Mode Crystal Range 20MHz ~ 6MHz 6MHz ~ 1MHz 1MHz ~ 100kHz 32.768kHz Oscillator Mode HXT XT LXT1 LXT2 Operating voltage range: Operating voltage: 2.2V~5.5V at -40C ~85C (Industrial) Operating frequency range (base on two clocks): Crystal mode: DC ~ 20MHz @ 5V DC ~ 8MHz @ 3V DC ~ 4MHz @ 2.2V ERC mode: DC ~ 16MHz @ 5V DC ~ 8MHz @ 3V DC ~ 4MHz @ 2.2V IRC mode: DC ~ 16MHz @ 4.5V~5.5V DC ~ 4MHz @ 2.2V~5.5V Programmable free running watchdog timer Package type: Three available interrupts: * * * * * * * * 14-pin DIP 300mil 14-pin SOP 150mil 16-pin DIP 300mil 16-pin SOP 300mil 18-pin DIP 300 mil 18-pin SOP 300mil 20-pin DIP 300mil 20-pin SSOP 209mil : : : : : : : : EM78F651NAPxS/xJ EM78F651NAMxS/xJ EM78F651NABPxS/xJ EM78F651NABMxS/xJ EM78F651NCPxS/xJ EM78F651NCMxS/xJ EM78F651NDPxS/xJ EM78F651NDKMxS/XJ * * * TCC overflow interrupt Input-port status changed interrupt (wake-up from sleep mode) External interrupt Green products do not contain hazardous substances. Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) *1 EM78F651N 8-Bit Microcontroller 3 Pin Assignment EM78F651NAP EM78F651NAN P53 P77/TCC /RESET VSS P60//INT P61 P62 P63 1 2 3 4 5 6 7 DIP SOP 14 13 12 11 10 9 8 P55/OSCI P54/OSCO VDD P67 P66 P65 P64 P77/TCC /RESET VSS P60//INT P61 P62 P63 EM78F651NBP EM78F651NBM 1 2 3 4 5 6 7 8 DIP SOP 16 15 14 13 12 11 10 9 P50 P55/OSCI P54/OSCO VDD P67 P66 P65 P64 EM78F651NCP EM78F651NCM P52 P53 P77/TCC /RESET VSS P60//INT P61 P62 P63 1 2 3 4 5 6 7 8 9 DIP SOP 18 17 16 15 14 13 12 11 10 P51 P50 P55/OSCI P54/OSC O VDD P67 P66 P65 P64 P56 P52 P53 P77/TCC /RESET VSS P60//INT P61 P62 P63 EM78F651NDKM EM78F651NDP 1 2 3 4 5 6 7 8 9 10 SSOP DIP 20 19 18 17 16 15 14 13 12 11 P57 P51 P50 P55/OSCI P54/OSCO VDD P67 P66 P65 P64 Fig. 3-1 Pin Assignment 2* Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller 4 Pin Description Table 1 EM78F651NAP, EM78F651NAM Symbol P54~P55 P60~P67 P77 OSCI Pin No. 13, 14 4~11 1 14 Type I/O I/O I/O I Function Bidirectional 2-bit input/output pins Bidirectional 8-bit input/output pins. These can be pulled-high or can be open drain by software programming. P60~63 can also be pulled down by software. P77 is an open drain I/O pin. Crystal type: Crystal input terminal or external clock input pin ERC type: RC oscillator input pin Crystal type: Output terminal for crystal oscillator or external clock input pin. RC type: Instruction clock output. External clock signal input. Real time clock/counter (with Schmitt Trigger input pin) must be tied to VDD or VSS if not in use. External interrupt pin triggered by a falling edge. Input pin with Schmitt Trigger. If this pin remains at logic low, the controller will also remain in reset condition. Power supply Ground OSCO 13 I/O TCC /INT /RESET VDD VSS 1 4 2 12 3 I I I - - Table 2 EM78F651NBP, EM78F651NBM Symbol P50, P53 P54~P55 P60~P67 P77 OSCI Pin No. 16, 1, 14, 15 5~12 2 15 Type I/O I/O I/O I Function Bidirectional 4-bit input/output pins 50, P53 can be pulled-down by software. Bidirectional 8-bit input/output pins. These can be pulled-high or can be open drain by software programming. P60~63 can also be pulled down by software. P77 is an open drain I/O pin. Crystal type: Crystal input terminal or external clock input pin ERC type: RC oscillator input pin Crystal type: Output terminal for crystal oscillator or external clock input pin. RC type: Instruction clock output. External clock signal input. The real time clock/counter (with Schmitt Trigger input pin) must be tied to VDD or VSS if not in use. External interrupt pin triggered by a falling edge. Input pin with Schmitt Trigger. If this pin remains at logic low, the controller will also remain in reset condition. Power supply Ground OSCO 14 I/O TCC /INT /RESET VDD VSS 2 5 3 13 4 I I I - Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) *3 EM78F651N 8-Bit Microcontroller Table 3 EM78F651NCP, EM78F651NCM Symbol P50~P53 P54~P55 P60~P67 P77 OSCI Pin No. 17, 18, 1 2, 15, 16 6~13 3 16 Type I/O I/O I/O I Function P50~P53 are bidirectional 4-bit input/output pins and can be pulleddown by software. Bidirectional 8-bit input/output pins. These can be pulled-high or can be open drain by software programming. P60~63 can also be pulled down by software. P77 is an open drain I/O pin. Crystal type: Crystal input terminal or external clock input pin ERC type: RC oscillator input pin Crystal type: Output terminal for crystal oscillator or external clock input pin. RC type: Instruction clock output. External clock signal input. Real time clock/counter (with Schmitt Trigger input pin) must be tied to VDD or VSS if not in use. External interrupt pin triggered by a falling edge. Input pin with Schmitt Trigger. If this pin remains at logic low, the controller will also remain in reset condition. Power supply Ground OSCO 15 I/O TCC /INT /RESET VDD VSS 3 6 4 14 5 I I I - Table 4 EM78F651NDKM, EM78F651NDP Symbol P50~P57 Pin No. 18, 19, 2, 3, 16, 17, 1, 20 7~14 4 17 Type I/O Function P50~P57 are bidirectional 8-it input/output pins. P50 and P51 can also be defined as the R-option pins. P50~P53 can be pulled-down by software. Bidirectional 8-bit input/output pins. These can be pulled-high or can be open drain by software programming. P60~63 can also be pulled down by software. P77 is an open drain I/O pin. Crystal type: Crystal input terminal or external clock input pin ERC type: RC oscillator input pin Crystal type: Output terminal for crystal oscillator or external clock input pin. RC type: Instruction clock output. External clock signal input. The real time clock/counter (with Schmitt Trigger input pin) must be tied to VDD or VSS if not in use. External interrupt pin triggered by a falling edge. Input pin with Schmitt Trigger. If this pin remains at logic low, the controller will also remain in reset condition. Power supply Ground P60~P67 P77 OSCI I/O I/O I OSCO 16 I/O TCC /INT /RESET VDD VSS 4 7 5 15 5 I I I - 4* Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller 5 Block Diagram Flash ROM PC Crystal Int. RC Ext. RC Instruction Register 5-level stack (13 bit) Oscillation Generator WDT Reset P7 P77 Instruction Decoder TCC TCC Mux ALU P6 P60 P61 P62 P63 P64 P65 P66 P67 R4 RAM ACC R3 (Status Reg.) Interrupt Control Register LVD LVR P5 P50 P51 P52 P53 P54 P55 P56 P57 Interrupt Circuit EEPROM Ext INT Fig. 5-1 Functional Block Diagram Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) *5 EM78F651N 8-Bit Microcontroller 6 Function Description 6.1 Operational Registers 6.1.1 R0 (Indirect Addressing Register) R0 is not a physically implemented register. It is used as an indirect addressing pointer. Any instruction using R0 as a pointer actually accesses data pointed by the RAM Select Register (R4). 6.1.2 R1 (Timer Clock/Counter) R1 is incremented by an external signal edge, which is defined by TE bit (CONT-4) through the TCC pin, or by the instruction cycle clock. It is writable and readable as any other registers. It is defined by resetting PSTE (CONT-3). The prescaler is assigned to TCC, if the PSTE bit (CONT-3) is reset. The contents of the prescaler counter are cleared only when the TCC register is written with a value. 6.1.3 R2 (Program Counter) & Stack Depending on the device type, R2 and hardware stack are 10-bit wide. The structure is depicted in Fig 6-1. The configuration structure generates 1024x13 bits on-chip Flash ROM addresses to the relative programming instruction codes. One program page is 1024 words long. R2 is set as all "0"s when under a reset condition. "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to go to any location within a page. "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page. "RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top-level stack. "ADD R2, A" allows a relative address to be added to the current PC, and the ninth and above bits of the PC will increase progressively. "MOV R2, A" allows to load an address from the "A" register to the lower 8 bits of the PC, and the ninth and tenth bits of the PC won't be changed. Any instruction except "ADD R2,A" that is written to R2 (e.g. "MOV R2, A", "BC R2, 6", etc.) will cause the ninth bit and the tenth bit (A8~A9) of the PC to remain unchanged. 6* Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller All instructions are single instruction cycle (fclk/2 or fclk/4) except for the instruction that would change the contents of R2. Such instruction will need one more instruction cycle. 000H 008H PC (A9 ~ A0) Reset Vector External INT pin interrupt vector Port 6 pin status change interrupt vector TCC overflow LVD interrupt vector User Memory Space Stack Level 1 Stack Level 2 Stack Level 3 Stack Level 5 On-chip Program Memory 3FFH Fig. 6-1 Program Counter Organization Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) *7 EM78F651N 8-Bit Microcontroller Address R PAGE Registers IOC PAGE Registers 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 1F 20 3F R0 R1 R2 R3 R4 R5 R6 R7 (IAR) (TCC) (PC) (Status) (RSR) (Port 5) (Port 6) (Port 7) Reserve Reserve IOC5 IOC6 IOC7 CONT Reserve (Control Register) Reserve Reserve Reserve (I/O Port Control Register) (I/O Port Control Register) (I/O Port Control Register) Reserve Reserve IOCA IOCB IOCC IOCD (WDT Control Register) (Pull-down Register) (Open-drain Control) (Pull-high Control Register) Reserve IOCF (Interrupt Mask Register) RA RB RC RD RE RF (WUCR) (EECON) (EEADR) (EEDATA) (LVD Control) (Interrupt Status) General Registers Bank 0 Bank 1 Fig. 6-2 Data Memory Configuration 8* Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller 6.1.4 R3 (Status Register) Bit 7 GP2 Bit 6 GP1 Bit 5 GP0 Bit 4 T Bit 3 P Bit 2 Z Bit 1 DC Bit 0 C Bits 7 ~ 5 (GP2 ~ 0): General-purpose read/write bits Bit 4 (T): Time-out bit Set to 1 with the "SLEP" and "WDTC" commands, or during power up and reset to 0 by WDT time-out. Bit 3 (P): Power down bit Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. Bit 2 (Z): Zero flag Set to "1" if the result of an arithmetic or logic operation is zero. Bit 1 (DC): Auxiliary carry flag Bit 0 (C): Carry flag 6.1.5 R4 (RAM Select Register) Bit 7: Bit 6 not used (read only). Bit 7 is always set to "0" at all time. is used to select Bank 0 or Bank 1. Bits 5~0 are used to select registers (address: 00~3F) in indirect addressing mode. Z flag of R3 is set to "1" when R4 content is equal to "3F." When R4=R4+1, R4 content will select as R0. See the configuration of the data memory in Fig 6-2. 6.1.6 R5 ~ R7 (Port 5 ~ Port 7) R5 and R6 are I/O registers. Only Bits 4, 5 of R5 are available (EM78F651NA) Only Bits 0, 1, 4, 5 of R5 are available (EM78F651NB) Only the lower 6 bits of R5 are available (EM78F651NC, D) Only Bit 0 of R7 is available 6.1.7 R8 ~ R9 Reserved registers Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) *9 EM78F651N 8-Bit Microcontroller 6.1.8 RA (Wake- up Control Register) Bit 7 Bit 6 ICWE Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - Bit 7: Not used. Set all "0" Bit 6 (ICWE): Port 6 input status change wake-up enable bit 0 = Disable Port 6 input status change wake-up 1 = Enable Port 6 input status change wake-up Bits 5~0: Not used. Set all to "0". 6.1.9 RB (EEPROM Control Register) Bit 7 RD Bit 6 WR Bit 5 EEWE Bit 4 EEDF Bit 3 EEPC Bit 2 Bit 1 Bit 0 - Bit 7: Read control register 0 : Does not execute EEPROM read 1 : Read EEPROM content, (RD can be set by software, RD is cleared by hardware after Read instruction is completed) Bit 6Write control register 0 : Write cycle to the EEPROM is complete. 1 : Initiate a write cycle, (WR can be set by software, WR is cleared by hardware after Write cycle is completed) Bit 5EEPROM Write Enable bit. 0 : Prohibit write to the EEPROM 1 : Allows EEPROM write cycles Bit 4EEPROM Detective Flag 0 : Write cycle is completed 1 : Write cycle is unfinished Bits 3EEPROM power-down control bit 0 : Switch off the EEPROM 1 : EEPROM is operating Bits 2 ~ 0: Not used, set to "0" at all time 10 * Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller 6.1.10 RC (128 Bytes EEPROM Address) Bit 7 Bit 6 EE_A6 Bit 5 EE_A5 Bit 4 EE_A4 Bit 3 EE_A3 Bit 2 EE_A2 Bit 1 EE_A1 Bit 0 EE_A0 Bit 7 Not used, fixed at "0" Bits 6 ~ 0 128 bytes EEPROM address 6.1.11 RD (128 Bytes EEPROM Data) Bit 7 EE_D7 Bit 6 EE_D6 Bit 5 EE_D5 Bit 4 EE_D4 Bit 3 EE_D3 Bit 2 EE_D2 Bit 1 EE_D1 Bit 0 EE_D0 Bits 7 ~ 0 128 bytes EEPROM data 6.1.12 RE (LVD Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 LVDEN Bit 2 /LVD Bit 1 LVD1 Bit 0 LVD0 Bits 7 ~ 4: Not used, set to "0" at all time Bit 3 (LVDEN): Low Voltage Detect Enable Bit 0 : LVD disable 1 : LVD enable Bit 2 (/LVD): Low Voltage Detector. This is a read only bit. When the VDD pin voltage is lower than LVD voltage interrupt level (selected by LVD1 and LVD0), this bit will be cleared. 0 : low voltage is detected 1 : low voltage is not detected or LVD function is disabled Bit 1~Bit 0 (LVD1~LVD0): Low Voltage Detect level select bits LVD1 0 0 1 1 LVD0 0 1 0 1 LVD Voltage Interrupt Level 2.1 3.1 3.8 4.3 Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) * 11 EM78F651N 8-Bit Microcontroller 6.1.13 RF (Interrupt Status Register) Bit 7 LVDIF Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 EXIF Bit 1 ICIF Bit 0 TCIF Note: " 1 " means with interrupt request " 0 " means no interrupt occurs Bit 7 (LVDIF): Low voltage Detector interrupt flag When LVD1, LVD0 = "0, 0", Vdd > 2.3V, LVDIF is "0", Vdd 2.3V, set LVDIF to "1". LVDIF reset to "0" by software. When LVD1, LVD0 = "0, 1", Vdd > 3.3V, LVDIF is "0", Vdd 3.3V, set LVDIF to "1". LVDIF reset to "0" by software. When LVD1, LVD0 = "1, 0", Vdd > 4.0V, LVDIF is "0", Vdd 4.0V, set LVDIF to "1". LVDIF reset to "0" by software. When LVD1, LVD0 = "1, 1", Vdd > 4.5V, LVDIF is "0", Vdd 4.5V, set LVDIF to "1". LVDIF reset to "0" by software. Bits 6 ~ 3 Not used. Set all to"0". Bit 2 (EXIF) External interrupt flag. Set by a falling edge on /INT pin, reset by software. Bit 1 (ICIF) Port 6 input status change interrupt flag. Set when Port 6 input changes, reset by software. Bit 0 (TCIF) TCC overflow interrupt flag. Set when TCC overflows, reset by software. RF can be cleared by instruction but cannot be set. IOCF is the interrupt mask register. Note that the result of reading RF is the "logic AND" of RF and IOCF. 6.1.14 R10 ~ R3F All of these are 8-bit general-purpose registers. 12 * Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller 6.2 Special Function Registers 6.2.1 A (Accumulator) Internal data transfer operation, or instruction operand holding usually involves the temporary storage function of the Accumulator, which is not an addressable register. 6.2.2 CONT (Control Register) Bit 7 Bit 6 /INT Bit 5 TS Bit 4 TE Bit 3 PSTE Bit 2 PST2 Bit 1 PST1 Bit 0 PST0 Bit 7 Not used, set to "0" at all time. Bit 6 (/INT): Interrupt enable flag 0 : masked by DISI or hardware interrupt 1 : enabled by ENI/RETI instructions Bit 5 (TS): TCC signal source 0 : internal instruction cycle clock 1 : transition on TCC pin Bit 4 (TE): TCC signal edge 0 : increment if a transition from low to high takes place on TCC pin 1 : increment if a transition from high to low takes place on TCC pin Bit 3 (PSTE): Prescaler enable bit for TCC 0 : prescaler disable bit, TCC rate is 1:1 1 : prescaler enable bit, TCC rate is set as Bit 2~Bit 0 Bit 0 (PST0) ~ Bit 2 (PST2): TCC prescaler bits PST2 0 0 0 0 1 1 1 1 PST1 0 0 1 1 0 0 1 1 PST0 0 1 0 1 0 1 0 1 TCC Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 CONT register is both readable and writable. Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) * 13 EM78F651N 8-Bit Microcontroller 6.2.3 IOC5 ~ IOC7 (I/O Port Control Register) A value of "1" sets the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output. Only Bits 4, 5 of R5 are available (EM78F651NA) Only Bits 0, 3, 4, 5 of IOC5 can be defined (EM78F651NB) Only the lower 6 bits of IOC5 can be defined (EM78F651NC) Only Bit 0 of IOC7 is available, when P7.0 is set as output, a pull-high resistor must be tied to Vdd, since this is an internal open-drain circuit. IOC5 and IOC7 registers are both readable and writable. 6.2.4 IOCA (WDT Control Register) Bit 7 WDTE Bit 6 EIS Bit 5 Bit 4 Bit 3 PSWE Bit 2 PSW2 Bit 1 PSW1 Bit 0 PSW0 Bit 7 (WDTE) Control bit used to enable the Watchdog timer 0 : Disable WDT 1 : Enable WDT WDTE is both readable and writable. Bit 6 (EIS): Control bit used to define the function of P60 (/INT) pin 0 : P60, bidirectional I/O pin 1 : /INT, external interrupt pin. In this case, the I/O control bit of P60 (Bit 0 of IOC6) must be set to "1". When EIS is "0", the path of /INT is masked. When EIS is "1", the status of /INT pin can also be read by way of reading Port 6 (R6). Refer to Fig 6-5 (a). EIS is both readable and writable. Bits 5~4: Not used, set to "0" at all time Bit 3 (PSWE): Prescaler enable bit for WDT 0 : prescaler disable bit, WDT rate is 1:1 1 : prescaler enable bit, WDT rate is set as Bit 0~Bit 2 Bit 2 (PSW2) ~ Bit 0 (PSW0): WDT prescaler bits PSW2 0 0 0 0 1 1 1 1 14 * PSW1 0 0 1 1 0 0 1 1 PSW0 0 1 0 1 0 1 0 1 WDT Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller 6.2.5 IOCB (Pull-down Control Register) Bit 7 /PD7 Bit 6 /PD6 Bit 5 /PD5 Bit 4 /PD4 Bit 3 /PD3 Bit 2 /PD2 Bit 1 /PD1 Bit 0 /PD0 Bit 7 (/PD7): Control bit used to enable the of P63 pull-down pin 0 : Enable internal pull-down 1 : Disable internal pull-down Bit 6 (/PD6): Control bit used to enable the P62 pull-down pin Bit 5 (/PD5): Control bit used to enable the P61 pull-down pin Bit 4 (/PD4): Control bit used to enable the P60 pull-down pin Bit 3 (/PD3): Control bit used to enable the P53 pull-down pin Bit 2 (/PD2): Control bit used to enable the P52 pull-down pin Bit 1 (/PD1): Control bit used to enable the P51 pull-down pin Bit 0 (/PD0): Control bit used to enable the P50 pull-down pin The IOCB Register is both readable and writable. 6.2.6 IOCC (Open-drain Control Register) Bit 7 OD7 Bit 6 OD6 Bit 5 OD5 Bit 4 OD4 Bit 3 OD3 Bit 2 OD2 Bit 1 OD1 Bit 0 OD0 Bit 7 (OD7): Control bit used to enable the open-drain output of P67 pin 0 : Disable open-drain output 1 : Enable open-drain output Bit 6 (OD6): Control bit used to enable the open-drain output of P66 pin Bit 5 (OD5): Control bit used to enable the open-drain output of P65 pin Bit 4 (OD4): Control bit used to enable the open-drain output of P64 pin Bit 3 (OD3): Control bit used to enable the open-drain output of P63 pin Bit 2 (OD2): Control bit used to enable the open-drain output of P62 pin Bit 1 (OD1): Control bit used to enable the open-drain output of P61 pin Bit 0 (OD0): Control bit used to enable the open-drain output of P60 pin The IOCC Register is both readable and writable. Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) * 15 EM78F651N 8-Bit Microcontroller 6.2.7 IOCD (Pull-high Control Register) Bit 7 /PH7 Bit 6 /PH6 Bit 5 /PH5 Bit 4 /PH4 Bit 3 /PH3 Bit 2 /PH2 Bit 1 /PH1 Bit 0 /PH0 Bit 7 (/PH7): Control bit used to enable the P67 pull-high pin. 0 : Enable internal pull-high 1 : Disable internal pull-high Bit 6 (/PH6): Control bit used to enable the P66 pull-high pin Bit 5 (/PH5): Control bit used to enable the P65 pull-high pin Bit 4 (/PH4): Control bit used to enable the P64 pull-high pin Bit 3 (/PH3): Control bit used to enable the P63 pull-high pin Bit 2 (/PH2): Control bit used to enable the P62 pull-high pin Bit 1 (/PH1): Control bit used to enable the P61 pull-high pin Bit 0 (/PH0): Control bit used to enable the P60 pull-high pin The IOCD Register is both readable and writable. 6.2.8 IOCF (Interrupt Mask Register) Bit 7 LVDIE Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 EXIE Bit 1 ICIE Bit 0 TCIE Bit 7 (LVDIE): LVDIF interrupt enable bit 0 : disable LVDIF interrupt 1 : enable LVDIF interrupt Bits 6~3: Not used, set to "0" at all time Bit 2 (EXIE): EXIF interrupt enable bit 0 : disable EXIF interrupt 1 : enable EXIF interrupt Bit 1 (ICIE): ICIF interrupt enable bit 0 : disable ICIF interrupt 1 : enable ICIF interrupt Bit 0 (TCIE): TCIF interrupt enable bit 0 : disable TCIF interrupt 1 : enable TCIF interrupt 16 * Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller Individual interrupt is enabled by setting its associated control bit in the IOCF to "1". Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Fig 6-8. The IOCF register is both readable and writable. 6.3 TCC/WDT & Prescaler There are two 8-bit counters available as prescalers for the TCC and WDT respectively. The PST0~PST2 bits of the CONT register are used to determine the ratio of the prescaler of TCC. Likewise, the PSW0~PSW2 bits of the IOCE0 register are used to determine the WDT prescaler. The prescaler counter will be cleared by the instructions each time they are written into TCC. The WDT and prescaler will be cleared by the "WDTC" and "SLEP" instructions. Fig 6-3 depicts the circuit diagram of TCC/WDT. R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be internal clock or external signal input (edge selectable from the TCC pin). If TCC signal source is from the internal clock, TCC will be incremented by 1 at every instruction cycle (without prescaler). As illustrated in Fig 6-3, selection of CLK=Fosc/2 or CLK=Fosc/4 depends on the Code Option bit 1 Note: VDD=5V, WDT time-out period = 16.5ms 8% VDD=3V WDT time-out period = 18ms 8%. * 17 Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller (I O C C 1) PST2~PST0 PSW0~PSW2 Fig. 6-3 Block Diagram of TCC and WDT Table 5 Internal RC Drift Rate (Ta=25C, VDD=2.3V~5.5 V, VSS=0V) Drift Rate Internal RC Temperature (-40C~85C) 3% 3% Voltage 5V 3V Process 5% 5% Total 8% 8% 16.5 ms 18 ms 6.4 I/O Ports The I/O registers, Port 5, Port 6 and Port 7, are bidirectional tri-state I/O ports. Port 6 can be pulled high internally by software. In addition, Port 6 can also have opendrain output by software. Input status change interrupt (or wake-up) function on Port 6 P50 ~ P53 and P60 ~ P63 pins can be pulled down by software. Each I/O pin can be defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC7). When Port 7.0 is set as output, the internal circuit becomes open-drain, so it must be tied to pullhigh to work normally. The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for Port 5, Port 6 and Port 7 are shown in the following Figures 6-4, 6-5 (a), 6-5 (b), and Figure 6-6. 18 * Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller PCRD Q _ Q P R C L D CLK PCWR PORT Q _ Q P R C L D CLK PDWR IOD PDRD 0 1 M U X Note: Pull-down is not shown in the figure. Fig. 6-4 Port 5 and Port 7.0 I/O Port and I/O Control Register Circuit PCRD Q _ Q PD R CLK C L PCWR P60 /INT PORT Bit 6 of IOCE DPQ R CLK _ C LQ 0 1 M U X PDRD Q _ Q P RD CLK C L PDWR IOD T10 P D RQ CLK _ C LQ INT Note: Pull-high (down) and Open-drain are not shown in the figure. Fig. 6-5 (a) P60 (/INT) I/O Port and I/O Control Register Circuit Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) * 19 EM78F651N 8-Bit Microcontroller PCRD Q _ Q P RD CLK C L PCWR P61~P67 PORT Q _ Q 0 1 P RD CLK C L IOD PDWR M U X TIN PDRD D P R CLK C L Q _ Q Note: Pull-high (down) and Open-drain are not shown in the figure. Fig. 6-5 (b) P61~P67 I/O Port and I/O Control Register Circuit IOCE.1 D P R Q Interrupt RE.1 ENI Instruction CLK _ CQ L T10 T11 P DRQ CLK _ CQ L P QRD CLK _ QC L T17 DISI Instruction Interrupt (Wake-up from SLEEP) /SLEP Next Instruction (Wake-up from SLEEP) Fig. 6-5 (c) Block Diagram of I/O Port 6 with Input Change Interrupt/Wake-up 20 * Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller Table 6 Usage of Port 6 Input Change Wake-up/Interrupt Function Usage of Port 6 Input Status Change Wake-up/Interrupt (I) Wake-up from Port 6 Input Status Change (a) Before Sleep 1. Disable WDT2 (use this very carefully) 2. Read I/O Port 6 (MOV R6,R6) 3 a. Enable interrupt (Set IOCF.1), after wake-up if "ENI" switch to interrupt vector (006H), if "DISI" excute next instruction 3 b. Disable interrupt (Set IOCF.1), always execute next instruction 4. Enable wake-up enable bit (Set RA.6) 5 a. Execute "SLEP" instruction b. After Wake-up 1. IF "ENI" Interrupt vector (006H) 2. IF "DISI" Next instruction (II) Port 6 Input Status Change Interrupt 1. Read I/O Port 6 (MOV R6,R6) 2. Execute "ENI" 3. Enable interrupt (Set IOCF.1) 4. IF Port 6 change (interrupt) Interrupt vector (006H) 6.5 Reset and Wake-up 6.5.1 Reset A reset is initiated by one of the following events: (1) Power-on reset (2) /RESET pin input "low", or (3) WDT time-out (if enabled) The device is kept in a reset condition for a period of approx. 18ms3 (one oscillator start-up timer period) after the reset is detected. And if the /Reset pin goes "low" or WDT time-out is active, a reset is generated, in RC mode the reset time is 34 clocks, High crystal mode reset time is 2ms and 32clocks. In low crystal mode, the reset time is 500ms. Once a reset occurs, the following functions are performed. Refer to Fig 6-7. The oscillator is running, or will be started. The Program Counter (R2) is set to all "0". All I/O port pins are configured as input mode (high-impedance state). The Watchdog timer and prescaler are cleared. 2 Note: Software disables WDT (watchdog timer) but hardware must be enabled before applying Port 6 Change Wake-Up function. (Code Option Register and Bit 11 (ENWDTB-) set to "1"). 3 Note: Vdd = 5V, set up time period = 16.8ms 8% Vdd = 3V, set up time period = 18ms 8% Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) * 21 EM78F651N 8-Bit Microcontroller When power is switched on, the upper three bits of R3 are cleared. The bits of the RB, RC, RD, RD, RE registers are set to their previous status. The bits of the CONT register are set to all "1" except for Bit 6 (INT flag). The bits of the IOCA register are set to all "1". The bits of the IOCB register are set to all "1". The IOCC register is cleared. The bits of the IOCD register are set to all "1". Bit 7 of the IOCE register is set to "1", and Bits 4 and 6 are cleared. Bits 0~2 of RF and Bits 0~2 of IOCF register are cleared. Sleep (power down) mode is asserted by executing the "SLEP" instruction. While entering sleep mode, WDT (if enabled) is cleared but keeps on running. After a wakeup, in RC mode the wake-up time is 34 clocks, High crystal mode wake-up time is 2 ms and 32 clocks. In low crystal mode, wake-up time is 500 ms. The controller can be awakened by: (1) External reset input on /RESET pin (2) WDT time-out (if enabled), or (3) Port 6 input status changes (if enabled) The first two cases will cause the EM78F651N to reset. The T and P flags of R3 can be used to determine the source of the reset (wake-up). The third case must set RA bit6, the 1 bit decide what's wake-up source to wake-up EM78F651N. Before SLEP instruction, enable the IOCF.1, the third case is considered the continuation of program execution and the global interrupt ("ENI" or "DISI" being executed) decides whether or not the controller branches to the interrupt vector following wake-up. If ENI is executed before SLEP, the instruction will begin to execute from the address 006H after wake-up. If DISI is executed before SLEP, the operation will restart from the succeeding instruction right next to SLEP after wake-up. In IOCF.1 disable before SLEP instruction, after wake-up EM78F651N will restart and execute next instruction sequentially. In Case 2, can be enabled before entering the sleep mode and Case 3, must be disabled. That is, [a] if Port 6 Input Status Change Interrupt and External interrupt(/INT) are enabled before SLEP, WDT must be disabled by software. However, the WDT bit in the option register remains enabled. Hence, the EM78F651N, can be awakened only by Case 1 or 3. 22 * Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller [b] If WDT is enabled before SLEP, Port 6 Input Status Change wake-up and External interrupt (/INT) must be disabled. Hence, the EM78F651N, can be awakened only by Case 1 or 2. Refer to the section on Interrupt. If Port 6 Input Status Change Interrupt is used to wake-up the EM78F651N, (Case [a] above), the following instructions must be executed before SLEP: MOV A, @xx000110b ; Select internal TCC clock CONTW CLR R1 WDTC ; Clear TCC and prescaler ; Clear WDT and prescaler MOV A, @0xxx1110b ; Select WDT prescaler & disable WDT IOW RA MOV R6, R6 ; Read Port 6 MOV A, @00000x1xb ; Enable Port 6 input change interrupt IOW RF ENI (or DISI) SLEP NOP One problem user should be aware of, is that after waking up from sleep mode, WDT would be enabled automatically. The WDT operation (being enabled or disabled) should be handled appropriately by software after waking up from sleep mode. ; Enable (or disable) global interrupt ; Sleep Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) * 23 EM78F651N 8-Bit Microcontroller Table 7 Summary of Registers Initialized Values Address Name Reset Type Bit Name Power-on N/A IOC5 /RESET and WDT Wake-up from Pin Change Bit Name Power-on N/A IOC6 /RESET and WDT Wake-up from Pin Change Bit Name Power-on N/A IOC7 /RESET and WDT Wake-up from Pin Change Bit Name Power-on N/A CONT /RESET and WDT Wake-up from Pin Change Bit Name Power-on 0x00 R0 (IAR) /RESET and WDT Wake-up from Pin Change Bit Name Power-on 0x01 R1 (TCC) /RESET and WDT Wake-up from Pin Change Bit Name Power-on 0x02 R2 (PC) /RESET and WDT Wake-up from Pin Change Bit 7 C57 1 1 P C67 1 1 P C77 1 1 P x 1 1 P U P P 0 0 P 0 0 *0/P Bit 6 C56 1 1 P C66 1 1 P U P P /INT 0 0 P U P P 0 0 P 0 0 *0/P Bit 5 C55 1 1 P C65 1 1 P U P P TS 1 1 P U P P 0 0 P 0 0 *0/P Bit 4 C54 1 1 P C64 1 1 P U P P TE 1 1 P U P P 0 0 P 0 0 *0/P Bit 3 C53 1 1 P C63 1 1 P U P P PAB 1 1 P U P P 0 0 P 0 0 *1/P Bit 2 C52 1 1 P C62 1 1 P U P P PSR2 1 1 P U P P 0 0 P 0 0 *0/P Bit 1 C51 1 1 P C61 1 1 P U P P PSR1 1 1 P U P P 0 0 P 0 0 *0/P Bit 0 C50 1 1 P C60 1 1 P U P P PSR0 1 1 P U P P 0 0 P 0 0 *0/P 24 * Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller Address Name Reset Type Bit Name Power-on Bit 7 GP2 0 0 P 0 0 0 P57 U P P P67 U P P P77 U P P 1 P P 0 0 0 Bit 6 GP1 0 0 P 0 0 0 P56 U P P P66 U P P x 0 0 0 1 P P ICWE 0 P P Bit 5 GP0 0 0 P U P P P55 U P P P65 U P P x 0 0 0 1 P P 0 0 0 Bit 4 T 1 t t U P P P54 U P P P64 U P P x 0 0 0 1 P P 0 0 0 Bit 3 P 1 t t U P P P53 U P P P63 U P P x 0 0 0 1 P P 0 0 0 Bit 2 Z U P P U P P P52 U P P P62 U P P x 0 0 0 1 P P 0 0 0 Bit 1 DC U P P U P P P51 U P P P61 U P P x 0 0 0 1 P P 0 0 0 Bit 0 C U P P U P P P50 U P P P60 U P P x 0 0 0 1 P P 0 0 0 0x03 R3 (SR) /RESET and WDT Wake-up from Pin Change Bit Name Power-on 0x04 R4 (RSR) /RESET and WDT Wake-up from Pin Change Bit Name Power-on 0x05 P5 /RESET and WDT Wake-up from Pin Change Bit Name Power-on 0x06 P6 /RESET and WDT Wake-up from Pin Change Bit Name Power-on 0x07 P7 /RESET and WDT Wake-up from Pin Change Bit Name Power-on 0x7~0x9 R7~R9 /RESET and WDT Wake-up from Pin Change Bit Name Power-on 0XA RA (WCR) /RESET and WDT Wake-up from Pin Change Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) * 25 EM78F651N 8-Bit Microcontroller Address Name Reset Type Bit Name Power-on Bit 7 RD 0 P P 0 0 0 Bit 6 WR 0 P P Bit 5 Bit 4 Bit 3 Bit 2 0 0 0 Bit 1 0 0 0 Bit 0 0 0 0 EEWE EEDF EEPC 0 P P 0 P P 0 P P 0XB RB (ECR) /RESET and WDT Wake-up from Pin Change Bit Name Power-on EE_A5 EE_A5 EE_A4 EE_A3 EE_A2 EE_A1 EE_A0 0 P P 0 P P 0 P P 0 P P 0 P P 0 P P 0 P P 0XC RC /RESET and WDT Wake-up from Pin Change Bit Name Power-on EE_D7 EE_D6 EE_D5 EE_D4 EE_D3 EE_D2 EE_D1 EE_D0 0 P P 0 0 0 LVDHIF 0 P P 0 0 0 x 0 U U 0 0 P /PD6 1 1 P 0 P P 0 0 0 x 0 U U 0 0 P /PD5 1 1 P 0 P P 0 0 0 x 0 U U 0 0 P /PD4 1 1 P 0 P P LVDEN 0 P P /LVD 1 1 P EXIF 0 0 P 0 0 P /PD2 1 1 P 0 P P LVD1 0 0 P ICIF 0 0 P 0 0 P /PD1 1 1 P 0 P P LVD0 0 0 P TCIF 0 0 P 0 0 P /PD0 1 1 P 0XD RD /RESET and WDT Wake-up from Pin Change Bit Name Power-on 0 0 P x 0 U U 0 0 P /PD3 1 1 P 0XE RE /RESET and WDT Wake-up from Pin Change Bit Name Power-on 0 0 P 0 0 P /PD7 1 1 P 0x0F RF(ISR) /RESET and WDT Wake-up from Pin Change Bit Name Power-on 0x0A IOCA /RESET and WDT Wake-up from Pin Change Bit Name Power-on 0x0B IOCB /RESET and WDT Wake-up from Pin Change 26 * Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller Address Name Reset Type Bit Name Power-on Bit 7 OD7 0 0 P /PH7 1 1 P WDTE 1 1 1 x 0 0 U U P P Bit 6 OD6 0 0 P /PH6 1 1 P EIS 0 0 P x 0 0 U U P P Bit 5 OD5 0 0 P /PH5 1 1 P x U U U x 0 0 U U P P Bit 4 OD4 0 0 P /PH4 1 1 P x 0 0 P x 0 0 U U P P Bit 3 OD3 0 0 P /PH3 1 1 P Bit 2 OD2 0 0 P /PH2 1 1 P Bit 1 OD1 0 0 P /PH1 1 1 P Bit 0 OD0 0 0 P /PH0 1 1 P 0x0C IOCC /RESET and WDT Wake-up from Pin Change Bit Name Power-on 0x0D IOCD /RESET and WDT Wake-up from Pin Change Bit Name Power-on PSWE PSW2 PSW1 PSW0 1 1 P x 0 0 U U P P 1 1 P EXIE 0 0 P U P P 1 1 P ICIE 0 0 P U P P 1 1 P TCIE 0 0 P U P P 0x0E IOCE /RESET and WDT Wake-up from Pin Change Bit Name Power-on 0x0F IOCF /RESET and WDT Wake-up from Pin Change Bit Name Power-on 0x10~0x2F R10~R2F /RESET and WDT Wake-up from Pin Change Legend: "x" = not used "u" = unknown or don't care "P" = previous value before reset "t" = check Table 8 * To jump Address 0x08, or to execute the instruction next to the "SLEP" instruction. 6.5.2 Status of RST, T, and P of the Status Register A reset condition is initiated by the following events: 1. Power-on condition 2. High-low-high pulse on /RESET pin 3. Watchdog timer time-out The values of T and P, listed in Table 8 are used to check how the processor wakes up. Table 9 shows the events that may affect the status of T and P. Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) * 27 EM78F651N 8-Bit Microcontroller Table 8 Values of RST, T and P after Reset Reset Type Power on /RESET during Operating mode /RESET wake-up during Sleep mode WDT during Operating mode WDT wake-up during Sleep mode Wake-Up on pin change during Sleep mode T 1 P 1 *P 1 0 0 1 *P 0 *P 0 0 * P: Previous status before reset Table 9 Status of T and P Being Affected by Events. Event Power on WDTC instruction WDT time-out SLEP instruction Wake-Up on pin change during SLEEP mode T 1 1 0 1 1 P 1 1 *P 0 0 * P: Previous value before reset VDD Oscillator D CLK CLR Q CLK Power-on Reset Voltage Detector WDTE WDT WDT Timeout Setup Time RESET /RESET Fig. 6-6 Block Diagram of Controller Reset 28 * Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller 6.6 Interrupt The EM78F651N, has three falling-edge interrupts listed below: (1) TCC overflow interrupt (2) Port 6 Input Status Change interrupt (3) External interrupt [(P60, /INT) pin] (4) LVD (Low Voltage Detector) interrupt RF is the interrupt status register that records the interrupt requests in the relative flags/bits. IOCF is the interrupt mask register. The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. When one of the enabled interrupts occurs, the next instruction will be fetched from address in the priority as shown in Table 10. Once in the interrupt service routine, the source of an interrupt can be determined by polling the flag bits in RF. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine and before interrupts are enabled to avoid recursive interrupts. When an interrupt is generated by the LVD (low voltage detector), in the code option enable LVD interrupt is selected, the next instruction will be fetched from address 00CH. When an interrupt is generated by the Timer clock/counter (if enabled), the next instruction will be fetched from address 009 (TCC). Before the Port 6 Input Status Change Interrupt is enabled, reading Port 6 (e.g. "MOV R6,R6") is necessary. Each Port 6 pin will have this feature if its status changes. The Port 6 Input Status Change Interrupt will wake up the EM78F651N from sleep mode if it is enabled prior to going into sleep mode by executing SLEP instruction. When wake-up occurs, the controller will continue to execute program in-line if the global interrupt is disabled. If the global interrupt is enabled, it will branch out to the interrupt vector 006H. External interrupt equipped with digital noise rejection circuit (input pulse less than 8 system clocks time is eliminated as noise), but in Low crystal oscillator (LXT) mode the noise rejection circuit will be disabled. When an interrupt (Falling edge) is generated by the External interrupt (when enabled), the next instruction will be fetched from address 003H. The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the status of its mask bit or the execution of ENI. Note that the outcome of RF will be the logic AND of RF and IOCF (refer to Fig 6-8). The RETI instruction ends the interrupt routine and enables the global interrupt (the execution of ENI). Before the interrupt subroutine is executed, the contents of ACC and the R3 and R4 register will be saved by hardware. If another interrupt occurred, the ACC, R3 and R4 will be replaced by the new interrupt. After the interrupt service routine is finished, ACC, R3 and R4 will be pushed back. Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) * 29 EM78F651N 8-Bit Microcontroller VCC D /IRQn CLK P R C L Q _ Q RFRD IRQn INT IRQm ENI/DISI RF Q _ Q P R C L D CLK IOCFWR IOD IOCF /RESET IOCFRD RFWR Fig. 6-7 Interrupt Input Circuit Interrupt Sources ENI/DISI ACC R3 R4 Interrupt occurs RETI STACKACC STACKR3 STACKR4 Fig. 6-8 Interrupt Back-up Diagram Table 10 Interrupt Vector Interrupt Vector 003H 006H 009H 00CH Interrupt Status External interrupt Port 6 pin change TCC overflow interrupt LVD interrupt Priority 1 2 3 4 Note: Priority is in descending order, i.e. 1 is the highest priority, 4 is the lowest priority 6.7 LVD (Low Voltage Detector) During power source unstable situations, such as external power noise interference or EMS test condition, it will cause the power to vibrate fiercely. At the time Vdd is unsettled, it is probably below the working voltage. When the system supply voltage, 30 * Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller Vdd, is below the working voltage, the IC kernel must keep all register status automatically. LVD property is set at Register RE, Bit 1, 0 detailed operation mode is as follows: Bits 1~Bit 0 (LVD1~LVD0): Low Voltage Detect level control Bits. LVD1 0 0 1 1 LVD0 0 1 0 1 LVD Voltage Interrupt Level 2.1 3.1 3.8 4.3 The LVD status and interrupt flag is referred to as RF Register RF Bit 7 LVDIF Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 EXIF Bit 1 ICIF Bit 0 TCIF Bit 7 (LVDIF): Low voltage Detector interrupt flag. When LVD1, LVD0 = "0, 0", Vdd > 2.3V, LVDIF is "0", Vdd 2.3V, set LVDIF to "1". LVDIF is reset to "0" by software. When LVD1, LVD0 = "0, 1", Vdd > 3.3V, LVDIF is "0", Vdd 3.3V, set LVDIF to "1". LVDIF is reset to "0" by software. When LVD1, LVD0 = "1, 0", Vdd > 4.0V, LVDIF is "0", Vdd 4.0V, set LVDIF to "1". LVDIF is reset to "0" by software. When LVD1, LVD0 = "1, 1", Vdd > 4.5V, LVDIF is "0", Vdd 4.5V, set LVDIF to "1". LVDIF is reset to "0" by software. The following steps are needed to setup the LVD function: Set the LVDEN of Register RE to "1", then use Bit 1, 0 (LVD1, LVD0) of Register RE to set LVD interrupt level Wait for LVD interrupt to occur. Clear LVD interrupt flag The internal LVD module uses internal circuit to fit. When the LVDEN is set to enable the LVD module, the current consumption will increase to about 10A. During sleep mode, the LVD module continues to operate. If the device voltage drops slowly and crosses the detect point, the LVDIF bit will be set and the device won't wake-up from Sleep mode. Until the other wake-up sources wake up the device, the LVD interrupt flag is still set at the prior status. When the system resets, the LVD flag will be cleared. Figure 6-9 shows the LVD module to detect the external voltage situation. When Vdd drops not below VLVD, LVDIF remain at "0". Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) * 31 EM78F651N 8-Bit Microcontroller When Vdd drops below VLVD, LVDIF is set to "1". If global ENI enable, LVDIF will be set to "1", the next instruction will branch to interrupt vector. The LVD interrupt flag is cleared to "0" by software. When Vdd drops below VRESET and is less than 80s, the system will all maintain the register status and system halt but oscillation is active. When Vdd drops below VRESET and is more than 80s, a system reset will occur, and for the following waveform situation, refer to Section 6.5.1 Reset Description. LVDXIF clear by software Vdd VLVD VRESET LVDXIF Internal Reset <50,40,30 us >50,40,30 us Vdd < Vreset not longer than 80us,system keep on going 18ms System occur reset Fig. 6-9 LVD Waveform Situation 6.8 Data EEPROM The Data EEPROM is readable and writable during normal operation over the whole Vdd range. The operation for Data EEPROM is base on a single byte. A write operation makes an erase-then-write cycle to take place on the allocated byte. The Data EEPROM memory provides high erase and write cycles. A byte write automatically erases the location and writes the new value. 6.8.1 Data EEPROM Control Register 6.8.1.1 RB (EEPROM Control Register) The EECR (EEPROM Control Register) is the control register for configuring and initiating the control register status. Bit 7 RD Bit 6 WR Bit 5 EEWE Bit 4 EEDF Bit 3 EEPC Bit 2 - Bit 1 - Bit 0 - Bit 7Read control register 0 : Does not execute EEPROM read 1 : Read EEPROM content, (RD can be set by software, RD is cleared by hardware after Read instruction is completed) Bit 6Write control register 0 : Write cycle to the EEPROM is complete. 1 : Initiate a write cycle, (WR can be set by software, WR is cleared by hardware after Write cycle is completed) 32 * Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller Bit 5EEPROM Write Enable bit 0 : Prohibit write to the EEPROM 1 : Allows EEPROM write cycles. Bit 4EEPROM Detect Flag 0 : Write cycle is completed 1 : Write cycle is unfinished Bit 3EEPROM power-down control bit 0 : Switch off the EEPROM 1 : EEPROM is operating Bits 2 ~ 0: Not used, set to "0" at all time 6.8.1.2 RC (128 Bytes EEPROM Address) When accessing the EEPROM data memory, the RC (128 bytes EEPROM address register) holds the address to be accessed. According the operation, the RD (128 bytes EEPROM Data register) holds the data to written, or the data read, at the address in RC. Bit 7 - Bit 6 EE_A6 Bit 5 EE_A5 Bit 4 EE_A4 Bit 3 EE_A3 Bit 2 EE_A2 Bit 1 EE_A1 Bit 0 EE_A0 Bit 7 Not used, fixed at "0". Bits 6 ~ 0 128 bytes EEPROM address 6.8.1.3 RD (128 Bytes EEPROM Data) Bit 7 EE_D7 Bit 6 EE_D6 Bit 5 EE_D5 Bit 4 EE_D4 Bit 3 EE_D3 Bit 2 EE_D2 Bit 1 EE_D1 Bit 0 EE_D0 Bits 7 ~ 0 128 bytes EEPROM data 6.8.2 Programming Step / Example Demonstration 6.8.2.1 Programming Step Follow these steps to write or read data from the EEPROM: (1) Set the RC.EEPC bit to 1 for enable EEPROM power. (2) Write the address to RC (128 bytes EEPROM address). a.1. Set the RC.EEWE bit to 1, if the write function is employed. a.2. Write the 8-bit data value to be programmed in the RD (128 bytes EEPROM data) a.3. Set the RC.WR bit to 1, then execute write function b. Set the RC.READ bit to 1, after which, execute read function (3) a. b. Wait for the RC.EEDF or RC.WR to be cleared Wait for the RC.EEDF to be cleared (4) For the next conversion, go to Step 2 as required. (5) If user wants to save power and to make sure the EEPROM data is not used, clear the RC.EEPC. Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) * 33 EM78F651N 8-Bit Microcontroller 6.8.2.2 Example Demonstration Programs ;To define the control register ;Write data to EEPROM RC == 0x0C RB == 0x0B RD == 0x0D Read == 0x07 WR == 0x06 EEWE == 0x05 EEDF == 0x04 EEPC == 0x03 BS RB, EEPC MOV A,@0x0A MOV RC,A BS RB, EEWE MOV A,@0x55 MOV RD,A BS RB,WR JBC RB,EEDF JMP $-1 ;To define the control register ;Read data from EEPROM RC == 0x0C RD == 0x0D Read == 0x07 WR == 0x06 EEWE == 0x05 EEDF == 0x04 EEPC == 0x03 BS RB, EEPC MOV A,@0x0A MOV RC,A BS RB, Read JBC RB,EEDF JMP $-1 MOV A,RD ; Assign the address from EEPROM ; Set EEPROM read function ; To check the EEPROM bit complete or not ; Set the EEPROM power on ; Set the data for EEPROM ; Write value to EEPROM ; To check the EEPROM bit complete or not ; Assign the address from EEPROM ; Enable the EEPROM write function ; Set the EEPROM power on 34 * Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller 6.9 Oscillator 6.9.1 Oscillator Modes The device can be operated in four different oscillator modes, such as Internal RC oscillator mode (IRC), External RC oscillator mode (ERC), High Crystal oscillator mode (HXT), and Low Crystal oscillator mode (LXT). User can select one of such modes by programming OSC2, OCS1 and OSC0 in the Code Option register. Table11 depicts how these four modes are defined. The up-limited operation frequency of the crystal/resonator on the different VDD is listed in Table 11 Table 11 Oscillator Modes defined by OSC2 ~ OSC0 Mode XT (Crystal oscillator mode) HXT (High Crystal oscillator mode) LXT1 (Low Crystal 1 oscillator mode) LXT2 (Low Crystal 2 oscillator mode) IRC mode, OSCO (P54) act as I/O pin IRC mode, OSCO (P54) act as RCOUT pin ERC mode, OSCO (P54) act as I/O pin ERC mode, OSCO (P54) act as RCOUT pin OSC2 0 0 0 0 1 1 1 1 OSC1 0 0 1 1 0 0 1 1 OSC0 0 1 0 1 0 1 0 1 NOTE 1. Frequency range of HXT mode is 20MHz ~ 6MHz. 2. Frequency range of XT mode is 6MHz ~ 1MHz. 3. Frequency range of LXT1 mode is 1MHz ~ 100kHz. 4. Frequency range of XT mode is 32kHz. Table 12 Summary of Maximum Operating Speeds Conditions Two cycles with two clocks VDD 2.5 3.0 5.0 Max Fxt. (MHz) 4.0 8.0 20.0 6.9.2 Crystal Oscillator/Ceramic Resonators (Crystal) The EM78F651N can be driven by an external clock signal through the OSCI pin as shown in Fig 6-10 below. OSCI OSCO EM78F651N Ext. Clock Fig. 6-10 Circuit for External Clock Input Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) * 35 EM78F651N 8-Bit Microcontroller In most applications, pin OSCI and pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation. Fig 6-11 depicts such circuit. The same thing applies whether it is in the HXT mode or in the LXT mode. Table 13 provides the recommended values of C1 and C2. Since each resonator has its own attribute, user should refer to its specification for appropriate values of C1 and C2. RS, a serial resistor, may be necessary for AT strip cut crystal or low frequency mode. C1 OSCI EM78F651N XTAL OSCO RS C2 Fig. 6-11 Circuit for Crystal/Resonator Table 13 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator Oscillator Type Frequency Mode Frequency 455kHz Ceramic Resonators HXT 2.0 MHz 4.0 MHz 32.768kHz LXT 100kHz 200kHz Crystal Oscillator HXT 455kHz 1.0MHz 2.0MHz 4.0MHz C1 (pF) 100~150 20~40 10~30 25 25 25 20~40 15~30 15 15 C2 (pF) 100~150 20~40 10~30 15 25 25 20~150 15~30 15 15 330 C OSCI EM78F651N Crystal Fig. 6-12 Circuit for Crystal/Resonator-Series Mode 330 7404 7404 7404 36 * Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller 4.7K 10K Vdd OSCI EM78F651N 7404 10K 7404 XTAL C1 C2 Fig. 6-13 Circuit for Crystal/Resonator-Parallel Mode 6.9.3 External RC Oscillator Mode For some applications that do not need a very precise timing calculation, the RC oscillator (Fig 6-14 ) offers a cost-effective oscillator configuration.. Nevertheless, it should be noted that the frequency of the RC oscillator is influenced by the supply voltage, the values of the resistor (Rext), the capacitor (Cext), and even by the operation temperature. Moreover, the frequency also changes slightly from one chip to another due to manufacturing process variation. In order to maintain a stable system frequency, the values of the Cext should not be less than 20pF, and that the value of Rext should not be greater than 1 M. If they cannot be kept in this range, the frequency is easily affected by noise, humidity, and leakage. The smaller the Rext in the RC oscillator, the faster its frequency will be. On the contrary, for very low Rext values, for instance, 1 K, the oscillator becomes unstable since the NMOS cannot discharge correctly the current of the capacitance. Based on the above reasons, it must be kept in mind that all of the supply voltage, the operation temperature, the components of the RC oscillator, the package types, and the PCB layout, will affect the system frequency. Vcc Rext OSCI EM78F651N Cext Fig. 6-14 Circuit for External RC Oscillator Mode * 37 Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller Table 14 RC Oscillator Frequencies Cext Rext 3.3k 20 pF 5.1k 10k 100k 3.3k 100 pF 5.1k 10k 100k 3.3k 300 pF 5.1k 10k 100k 1 2 Average Fosc 5V, 25C 3.3 MHz 2.27 MHz 1.1 MHz 145kHz 1.02 MHz 724kHz 360kHz 45kHz 400kHz 280kHz 143kHz 14kHz Average Fosc 3V, 25C 3 MHz 2.1 MHz 1.05 MHz 145kHz 0.98 MHz 694kHz 360kHz 47kHz 380kHz 270kHz 140kHz 14kHz Note: : Measured based on DIP packages. : The values are for design reference only. 6.9.4 Internal RC Oscillator Mode EM78F651N offers a versatile internal RC mode with default frequency value of 4MHz. Internal RC oscillator mode has other frequencies (1MHz, 8MHz and 455kHz) that can be set by Code Option (Word 1), RCM1 and RCM0. All these four main frequencies can be calibrated by programming the Code Option (Word 1) bits, C4~C0. Table 15 describes a typical instance of the calibration. Table 15 Internal RC Drift Rate (Ta=25C, VDD=5 V 5%, VSS=0V) Drift Rate Internal RC 4MHz 16MHz 3.58MHz 455kHz Temperature (-40C~85C) 3% 3% 3% 3% Voltage (2.3V~5.5V) 5% 5% 5% 5% Process 3% 5% 5% 5% Total 11% 13% 13% 13% Table 16 Calibration Selections for Internal RC Mode C4 1 1 1 1 1 1 1 1 C3 1 1 1 1 1 1 1 1 C2 1 1 1 1 0 0 0 0 C1 1 1 0 0 1 1 0 0 C0 1 0 1 0 1 0 1 0 *Cycle Time (ns) 399 385 371 358 347 336 326 316 *Frequency (MHz) 2.506 2.6 2.693 2.786 2.879 2.973 3.066 3.159 38 * Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller C4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C2 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 C0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 *Cycle Time (ns) 307 298 290 283 275 268 262 256 250 244 238 233 228 223 219 214 210 206 202 198 195 191 188 185 *Frequency (MHz) 3.253 3.346 3.439 3.533 3.626 3.719 3.813 3.906 4.00 4.093 4.186 4.279 4.373 4.466 4.559 4.653 4.746 4.839 4.933 5.026 5.119 5.213 5.306 5.4 * 1.Theoretical values, for reference only. It depend on process. 2. Similar way of calculation is also applicable for low frequency mode. 6.10 Code Option Register The EM78F651N has a Code option word that is not part of the normal program memory. The option bits cannot be accessed during normal program execution. Code Option Register and Customer ID Register arrangement distribution: Word 0 Bit 12~Bit 0 Word 1 Bit 12~Bit 0 Word 2 Bit 12~Bit 0 6.10.1 Code Option Register (Word 0) Word 0 Bit 12 - Bit 11 NRHL Bit 10 NRE Bit 9 CYES Bit 8 CLKS1 Bit 7 CLKS0 Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) * 39 EM78F651N 8-Bit Microcontroller Word 0 Bit 6 ENWDTB Bit 5 OSC2 Bit 4 OSC1 Bit 3 OSC0 Bit 2 PR2 Bit 1 PR1 Bit 0 PR0 Bit 12: Not used, set to "0" at all time. Bit 11 (NRHL): Noise rejection high/low pulse define bit. INT pin is falling edge trigger. 1 : Pulses equal to 8/fc [s] is regarded as signal 0 : Pulses equal to 32/fc [s] is regarded as signal (default) NOTE The noise rejection function is turned off in the LXT2 and sleep mode. Bit 10 (NRE): Noise rejection enable (depend on EM78F651N). INT pin is falling edge trigger. 1 : disable noise rejection 0 : enable noise rejection (default) but in Low Crystal oscillator (LXT) mode, the noise rejection circuit is always disabled Bit 9 (CYES): Instruction cycle selection bit 1 : one instruction cycle (default) 0 : two instruction cycles Bit 8~7 (CLKS1 and CLKS0): Instruction period option bit Instruction Period 4 clocks 2 clocks 8 clocks 16 clocks CLKS1 0 0 1 1 CLKS0 0 1 0 1 Refer to the section on Instruction Set. Bit 6 (ENWDTB): Watchdog timer enable bit 1 : Enable 0 : Disable Bits 5~3 (OSC2 ~ OSC0): Oscillator Mode Selection bits 40 * Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller Oscillator Modes defined by OSC2 ~ OSC0 Mode XT (Crystal oscillator mode) HXT (High Crystal oscillator mode) LXT1 (Low Crystal 1 oscillator mode) LXT2 (Low Crystal 2 oscillator mode) IRC mode, OSCO (P54) act as I/O pin IRC mode, OSCO (P54) act as RCOUT pin ERC mode, OSCO (P54) act as I/O pin ERC mode, OSCO (P54) act as RCOUT pin OSC2 0 0 0 0 1 1 1 1 OSC1 0 0 1 1 0 0 1 1 OSC0 0 1 0 1 0 1 0 1 Note: 1. Frequency range of HXT mode is 20MHz ~ 6MHz. 2. Frequency range of XT mode is 6MHz ~ 1MHz. 3. Frequency range of LXT1 mode is 1MHz ~ 100kHz. 4. Frequency range of LXT2 mode is 32kHz. Bit 2~0 (PR2~PR0): Protect Bit. PR2~PR0 are protect bits, protect type is as follows: PR2 1 1 1 1 0 0 0 0 PR1 1 1 0 0 1 1 0 0 PR0 1 0 1 0 1 0 1 0 Protect Enable Enable Enable Enable Enable Enable Enable Disable Word 1 Bit 12 - Bit 11 TCEN Bit 10 - Bit 9 SHE Bit 8 C4 Bit 7 C3 Word 1 Bit 6 C2 Bit 5 C1 Bit 4 C0 Bit 3 RCM1 Bit 2 RCM0 Bit 1 LVR1 Bit 0 LVR0 Bit 12: Not used, set to "1" at all time Bit 11(TCEN): TCC enable bit 0 : P77/TCC is set as P77 (default) 1 : P77/TCC is set as TCC Bit 10: Not used, set to "0" at all time. Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) * 41 EM78F651N 8-Bit Microcontroller Bit 9 (SHE): System Halt Enable Bit. 0 : Enable 1 : Disable Bits 8, 7, 6, 5 and Bit 4 ( C4, C3, C2, C1, C0 ): internal RC mode calibration bits. Calibration Selection for Internal RC Mode C4 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 C0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 *Cycle Time (ns) 399 385 371 358 347 336 326 316 307 298 290 283 275 268 262 256 250 244 238 233 228 223 219 214 210 206 202 198 195 191 188 185 *Frequency (MHz) 2.506 2.6 2.693 2.786 2.879 2.973 3.066 3.159 3.253 3.346 3.439 3.533 3.626 3.719 3.813 3.906 4.00 4.093 4.186 4.279 4.373 4.466 4.559 4.653 4.746 4.839 4.933 5.026 5.119 5.213 5.306 5.4 Note: 1. Theoretical values, an instance of the high frequency mode, are shown for reference only. It depends on the process. 2. Similar way of calculation is also applicable for low frequency mode. 42 * Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller Bit 3 and Bit 2 (RCM1, RCM0): RC mode selection bits RCM 1 0 0 1 1 RCM 0 0 1 0 1 *Frequency(MHz) 4 16 3.58 455kHz Bits 1~0 (LVR1 ~ LVR0): Low Voltage Reset Enable bits LVR1 0 0 1 1 LVR0 0 1 0 1 Reset Level NA 2.6V 3.3V 3.8V Release Level NA 2.8V 3.45V 3.9V LVR1, LVR0="0, 0" LVR disable, power- on reset point of EM78F651N is 2.0V. LVR1, LVR0="0, 1" If Vdd < 2.6V, the EM78F651N will be reset. LVR1, LVR0="1, 0" If Vdd < 3.3V, the EM78F651N will be reset. LVR1, LVR0="1, 1" If Vdd < 3.8V, the EM78F651N will be reset. 6.10.2 Customer ID Register (Word 2) Bit 12~Bit 0 XXXXXXXXXXXXX Bits 12~0: Customer's ID code 6.11 Power-on Considerations Any microcontroller is not guaranteed to start to operate properly before the power supply stays has stabilized. The EM78F651N has an on-chip Power-on Voltage Detector (POVD) with a detecting level of 2.0V. It will work well if Vdd can rise quick enough (50 ms or less). In many critical applications, however, extra devices are still required to assist in solving power-up problems. 6.12 External Power-on Reset Circuit The circuit shown in Fig 6-15 implements an external RC to produce a reset pulse. The pulse width (time constant) should be kept long enough for Vdd to reached minimum operation voltage. This circuit is used when the power supply has slow rise time. Because the current leakage from the /RESET pin is 5A, it is recommended that R should not be greater than 40 K. In this way, the /RESET pin voltage is held below 0.2V. The diode (D) acts as a short circuit at the moment of power down. Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) * 43 EM78F651N 8-Bit Microcontroller The capacitor C will discharge rapidly and fully. Rin, the current-limited resistor, will prevent high current or ESD (electrostatic discharge) from flowing to pin /RESET. Vdd /RESET EM78F651N Rin C R D Fig. 6-15 External Power-Up Reset Circuit 6.13 Residue-Voltage Protection When battery is replaced, device power (Vdd) is taken off but residue-voltage remains. The residue-voltage may trip below Vdd minimum, but not to zero. This condition may cause a poor power-on reset. Fig 6-16 and Fig 6-17 shows how to build a residue-voltage protection circuit. Vdd EM78F651N Q1 /RESET 40K 1N4684 10K 33K Vdd Fig. 6-16 Circuit 1 for the Residue Voltage Protection 44 * Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller Vdd EM78F651N Q1 /RESET 40K R2 R1 Vdd Fig. 6-17 Circuit 2 for the Residue Voltage Protection 6.14 Instruction Set Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands. Normally, all instructions are executed within one single instruction cycle (one instruction consists of two oscillator periods), unless the program counter is changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6", "CLR R2", etc.). In this case, the execution takes two instruction cycles. If for some reasons, the specification of the instruction cycle is not suitable for certain applications, try modifying the instruction as follows: (A) Change one instruction cycle to consist of four oscillator periods. (B) "JMP", "CALL", "RET", "RETL", "RETI", or the conditional skip ("JBS", "JBC", "JZ", "JZA", "DJZ", "DJZA") commands which were tested to be true, are executed within two instruction cycles. The instructions that are written to the program counter also take two instruction cycles. Case (A) is selected by the Code Option bit, called CLK. One instruction cycle consists of two oscillator clocks if CLK is low, and four oscillator clocks if CLK is high. Note that once the four oscillator periods within one instruction cycle is selected as in Case (A), the internal clock source to TCC should be CLK=Fosc/4, instead of Fosc / 2 as indicated in Fig 6-3. In addition, the instruction set has the following features: (1) Every bit of any register can be set, cleared, or tested directly. (2) The I/O register can be regarded as general register. That is, the same instruction can operate on the I/O register. Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) * 45 EM78F651N 8-Bit Microcontroller Convention: R = Register designator that specifies which one of the registers (including operation and general purpose registers) is to be utilized by the instruction. b = Bit field designator that selects the value for the bit located in the register R and which affects the operation. k = 8 or 10-bit constant or literal value Binary Instruction 0 0000 0000 0000 0 0000 0000 0001 0 0000 0000 0010 0 0000 0000 0011 0 0000 0000 0100 0 0000 0000 rrrr 0 0000 0001 0000 0 0000 0001 0001 0 0000 0001 0010 0 0000 0001 0011 0 0000 0001 0100 0 0000 0001 rrrr 0 0000 01rr rrrr 0 0000 1000 0000 0 0000 11rr rrrr 0 0001 00rr rrrr 0 0001 01rr rrrr 0 0001 10rr rrrr 0 0001 11rr rrrr 0 0010 00rr rrrr 0 0010 01rr rrrr 0 0010 10rr rrrr 0 0010 11rr rrrr 0 0011 00rr rrrr 0 0011 01rr rrrr 0 0011 10rr rrrr 0 0011 11rr rrrr 0 0100 00rr rrrr 0 0100 01rr rrrr Hex 0000 0001 0002 0003 0004 000r 0010 0011 0012 0013 0014 001r 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr Mnemonic NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET RETI CONTR IOR R MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R Operation No Operation Decimal Adjust A A CONT 0 WDT, Stop oscillator 0 WDT A IOCR Enable Interrupt Disable Interrupt [Top of Stack] PC [Top of Stack] PC, Enable Interrupt CONT A IOCR A AR 0A 0R R-A A R-A R R-1 A R-1 R ARA ARR A&RA A&RR ARA ARR A+RA A+RR RA RR Status Affected None C None T, P T, P None 1 None None None None None None 1 None Z Z Z, C, DC Z, C, DC Z Z Z Z Z Z Z Z Z, C, DC Z, C, DC Z Z 46 * Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller Binary Instruction 0 0100 10rr rrrr 0 0100 11rr rrrr 0 0101 00rr rrrr 0 0101 01rr rrrr 0 0101 10rr rrrr 0 0101 11rr rrrr 0 0110 00rr rrrr 0 0110 01rr rrrr 0 0110 10rr rrrr 0 0110 11rr rrrr 0 0111 00rr rrrr 0 0111 01rr rrrr 0 0111 10rr rrrr 0 0111 11rr rrrr 0 100b bbrr rrrr 0 101b bbrr rrrr 0 110b bbrr rrrr 0 111b bbrr rrrr 1 00kk kkkk kkkk 1 01kk kkkk kkkk 1 1000 kkkk kkkk 1 1001 kkkk kkkk 1 1010 kkkk kkkk 1 1011 kkkk kkkk 1 1100 kkkk kkkk 1 1101 kkkk kkkk 1 1111 kkkk kkkk 1 1110 1001 000k 1 Hex 04rr 04rr 05rr 05rr 05rr 05rr 06rr 06rr 06rr 06rr 07rr 07rr 07rr 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1Fkk 1E9k Mnemonic COMA R COM R INCA R INC R DJZA R DJZ R RRCA R RRC R RLCA R RLC R SWAPA R SWAP R JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k ADD A,k BANK k Operation /R A /R R R+1 A R+1 R R-1 A, skip if zero R-1 R, skip if zero R(n) A(n-1), R(0) C, C A(7) R(n) R(n-1), R(0) C, C R(7) R(n) A(n+1), R(7) C, C A(0) R(n) R(n+1), R(7) C, C R(0) R(0-3) A(4-7), R(4-7) A(0-3) R(0-3) R(4-7) R+1 A, skip if zero R+1 R, skip if zero 0 R(b) 1 R(b) if R(b)=0, skip if R(b)=1, skip PC+1 [SP], (Page, k) PC (Page, k) PC kA AkA A&kA AkA k A, [Top of Stack] PC k-A A k+A A K->R3(6) Status Affected Z Z Z Z None None C C C C None None None None None 2 None 3 None None None None None Z Z Z None Z, C, DC Z, C, DC None Note: This instruction is applicable to IOC5~IOC6, IOCB ~ IOCF only. 2 3 This instruction is not recommended for RF operation. This instruction cannot operate under RF. Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) * 47 EM78F651N 8-Bit Microcontroller 7 Timing Diagrams AC Test Input/Output Waveform 0.9Vdd 0.7Vdd 0.25Vdd TEST POINTS 0.75Vdd 0.25Vdd 0.1Vdd AC Testing : Input is driven at 0.9Vdd for logic "1",and 0.1Vdd for logic "0".Timing measurements are made at 0.75Vdd for logic "1",and 0.25Vdd for logic "0". RESET Timing (CLK="0") NOP Instruction 1 Executed CLK /RESET Tdrh TCC Input Timing (CLKS="0") Tins CLK TCC Ttcc 48 * Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller 8 Absolute Maximum Ratings EM78F651N Items Temperature under bias Storage temperature Working voltage Working frequency Input voltage Output voltage 0C to 70C -65C to 150C 2.2 to 5.5V DC to 20MHz* Vss-0.3V to Vdd+0.5V Vss-0.3V to Vdd+0.5V Rating Note: These parameters are theoretical values and have not been tested. 9 DC Electrical Characteristic Ta=25 C, VDD=5.0V5%, VSS=0V Parameter Crystal: VDD to 3V Crystal: VDD to 5V Fxt ERC: VDD to 5V IRC: VDD to 5 V IIL IRC1 IRCE IRC2 IRC3 IRC4 Symbol Condition Two cycles with two clocks R: 5.1K, C: 100 pF 4MHz, 1MHz, 455kHz, 8MHz Min DC DC F30% F30% - 2.9 4.3 Typ 10 20 830 F - 4 4.5 16 3.58 455 4 22 1.8 17 0 - - - - Max 14 24 F30% F30% 1 5.7 4.7 22 5.15 645 4.1 23 1.9 18 1 Vdd+0.3V Unit MHz MHz kHz Hz A MHz % MHz MHz kHz V mA V mA A V V V V Input Leakage Current for input pins VIN = VDD, VSS IRC: VDD to 5V Internal RC oscillator error per stage IRC: VDD to 5V IRC: VDD to 5V IRC: VDD to 5V Input High Threshold Voltage (Schmitt Trigger) Sink current Input Low Threshold Voltage (Schmitt Trigger) Sink current RCM0:RCM1=1:0 RCM0:RCM1=0:1 RCM0:RCM1=1:1 OSCI in RC mode VI from low to high, VI=5V OSCI in RC mode VI from high to low, VI=2V RCM0:RCM1=0:0 11.6 2.5 330 3.9 21 1.7 16 -1 0.75Vdd VIHRC IERC1 VILRC IERC2 IIL VIH1 VIL1 VIHT1 VILT1 Input Leakage Current for input pins VIN = VDD, VSS Input High Voltage (Schmitt Trigger) Ports 5, 6, 7 Input Low Voltage (Schmitt Trigger) Input High Threshold Voltage (Schmitt Trigger) Input Low Threshold Voltage (Schmitt Trigger) Ports 5, 6, 7 /RESET /RESET -0.3V 0.75Vdd 0.25Vdd Vdd+0.3V -0.3V 0.25Vdd Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) * 49 EM78F651N 8-Bit Microcontroller Symbol VIHT2 VILT2 VIHX1 VILX1 IOH1 IOL1 IOL2 IPH IPL Parameter Input High Threshold Voltage (Schmitt Trigger) Input Low Threshold Voltage Schmitt Trigger) Clock Input High Voltage Clock Input Low Voltage Output High Voltage (Ports 5, 6) Output Low Voltage (Ports 5, 7) Output Low Voltage (Ports 6) Pull-high current Pull-low current TCC, INT TCC, INT Condition Min 0.75Vdd Typ - Max Vdd+0.3V Unit V V V V mA mA mA A A -0.3V 2.9 1.7 - - - -45 5 - 3.0 1.8 -3.5 10 18 -65 25 0.25Vdd 3.1 1.9 - - - -85 40 OSCI in crystal mode OSCI in crystal mode VOH = VDD-0.5V VOL = GND+0.5V VOL = GND+0.5V Pull-high active, input pin at VSS Pull-low active, Input pin at Vdd All input and I/O pins at VDD, Output pin floating, WDT disabled All input and I/O pins at VDD, Output pin floating, WDT enabled /RESET= 'High', Fosc=32kHz (Crystal type, CLKS="0"), Output pin floating, WDT disabled /RESET= 'High', Fosc=32kHz (Crystal type, CLKS="0"), Output pin floating, WDT enabled /RESET= 'High', Fosc=4MHz (Crystal type, CLKS="0"), Output pin floating, WDT enabled /RESET= 'High', Fosc=10MHz (Crystal type, CLKS="0"), Output pin floating, WDT enabled ISB1 Power down current - 1.0 2.0 A ISB2 Power down current - 850 1000 A ICC1 Operating supply current at two clocks 12 15 20 A ICC2 Operating supply current at two clocks - 300 350 A ICC3 Operating supply current at two clocks - 1.3 1.6 mA ICC4 Operating supply current at two clocks - 2.7 3.0 mA Note: These parameters are theoretical values and have not been tested. * Data in the Minimum, Typical, Maximum ("Min", "Typ", "Max") columns are based on characterization results at 25C. This data is for design guidance only and is not tested. 50 * Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller LVD (Low Voltage Detector) Electrical Characteristics Symbol LVD1 LVD2 LVD3 LVD4 Note: Parameter LVD1 Voltage interrupt level(Schmitt trigger) LVD2 Voltage interrupt level(Schmitt trigger) LVD3 Voltage interrupt level(Schmitt trigger) LVD4 Voltage interrupt level(Schmitt trigger) Condition Vdd=5V Vdd=5V Vdd=5V Vdd=5V Min.* 2.1+0.1 3.1+0.1 3.8+0.1 4.3+0.1 Typ. Max.** 2.2+0.1 3.3+0.1 3.9+0.1 4.4+0.1 Unit V V V V *VDD Voltage from High to Low. ** VDD Voltage from Low to High. LVR (Low Voltage Reset) Electrical Characteristics Symbol LVR1 LVR2 LVR3 LVR4 Note: Parameter LVR1 Voltage reset level (Schmitt trigger) LVR2 Voltage reset level (Schmitt trigger) LVR3 Voltage reset level (Schmitt trigger) LVR4 Voltage reset level (Schmitt trigger) Condition Vdd=5V Vdd=5V Vdd=5V Vdd=5V Min.* - 2.6+0.15 3.3+0.15 3.8+0.15 Typ. - - - - Max.** - 2.8+0.15 3.45+0.15 3.9+0.15 Unit V V V V *VDD Voltage from High to Low. ** VDD Voltage from Low to High. Data EEPROM Electrical Characteristics Symbol Tprog Treten Tendu Parameter Erase/Write cycle time Data Retention Endurance time Condition Vdd = 2.0~ 5.5V Temperature = -40C ~ 85C Min. - - - Typ. 6 10 100K Max. - - - Unit ms Years Cycles Program Flash memory Electrical Characteristics Symbol Tprog Treten Tendu Parameter Erase/Write cycle time Data Retention Endurance time Condition Vdd = 5.0V Temperature = -40C ~ 85C Min. - - - Typ. 4 10 100K Max. - - - Unit ms Years Cycles Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) * 51 EM78F651N 8-Bit Microcontroller 10 AC Electrical Characteristic EM78F651N, 0 Ta 70C, VDD=5V, VSS=0V -40 Ta 85C, VDD=5V, VSS=0V Symbol Dclk Tins Ttcc Tdrh Trst Twdt Tset Thold Tdelay Parameter Input CLK duty cycle Instruction cycle time (CLKS="0") TCC input period Device reset hold time /RESET pulse width Watchdog timer period Input pin setup time Input pin hold time Output pin delay time Conditions - Crystal type RC type - - Ta = 25C Ta = 25C - - Cload=20pF Min 45 100 500 (Tins+20)/N* 11.8 2000 11.8 - - - Typ 50 - - - 16.8 - 16.8 0 20 50 Max 55 DC DC - 21.8 - 21.8 - - - Unit % ns ns ns ms ns ms ns ns ns Note: These parameters are theoretical values and have not been tested. * Data in the Minimum, Typical, Maximum ("Min", "Typ", "Max") columns are based on characterization results at 25C. This data is for design guidance only and is not tested. * N = selected prescaler ratio 52 * Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) EM78F651N 8-Bit Microcontroller APPENDIX A Package Type Flash MCU EM78F651NAP EM78F651NAPS/NAPJ EM78F651NAM EM78F651NAMS/NAMJ EM78F651NBP EM78F651NBPS/NBPJ EM78F651NBM EM78F651NBMS/NBMJ EM78F651NCP EM78F651NCPS/NCPJ EM78F651NCM EM78F651NCMS/NCMJ EM78F651NDKM EM78F651NDKMS/NDKMJ EM78F651NDP EM78F651NDPS/NDPJ Package Type DIP DIP SOP SOP DIP DIP SOP SOP DIP DIP SOP SOP SSOP SSOP DIP DIP Pin Count 14 14 14 14 16 16 16 16 18 18 18 18 20 20 20 20 Package Size 300 mil 300 mil 150 mil 150 mil 300 mil 300 mil 300 mil 300 mil 300 mil 300 mil 300 mil 300 mil 209 mil 209 mil 300mil 300mil Green products do not contain hazardous substances. The third edition of Sony SS-00259 standard. Pb contents should be less the 100ppm Pb contents comply with Sony specs. Part no. Electroplate type Ingredient (%) Melting point (C) Electrical resistivity ( cm) Hardness (hv) Elongation (%) EM78F651xS/xJ Pure Tin Sn:100% 232C 11.4 8~10 >50% Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) * 53 EM78F651N 8-Bit Microcontroller B ICE 652N Output Pin Assignment (JP 3) P77/TCC P60/INT /RESET GND P52 P61 P64 P56 P53 P62 2 4 3 6 5 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 7 P55/OSCI 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 P54/OSCO JP 3 1 P57 VCC P50 P63 P65 P66 C EM78F651N Program Pin: In the following IC diagram, "Pin # number" means the Pin to be connected to the Socket in DWTR. P51 EM78F651NDKM P56 P52 P53 P77/TCC PIN#15 PIN#16 /RESET VSS P60/I P61 P62 P63 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 P57 P51 P50 P55/OSCI P54/OSCO VDD P67 P66 P65 P64 PIN#25 PIN#28 PIN#29 54 * P77 P67 Product Specification (V1.1) 10.20.2006 (This specification is subject to change without further notice) |
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